Semiconductor device having porous structure

ABSTRACT

A semiconductor device having a hollow structure includes: a substrate on which a wiring layer is formed; a low-dielectric layer with a porosity of 6% to 25% having vias and trenches and having voids between adjacent vias; and a contact layer of copper with which the vias and trenches are filled. The contact layer is in contact with the wiring layer and an upper surface of the contact layer is exposed from the dielectric layer.

This is a divisional application of U.S. patent application Ser. No.10/693,200, filed Oct. 24, 2003, which claims the benefit of U.S.Provisional Application No. 60/422,956, field Oct. 31, 2002, thedisclosure of which is incorporated herein by reference in theirentirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a technology of manufacturing semiconductordevices having a porous structure and voids (air-gaps), and particularlyrelates to a technology that involve selectively etching a sacrificialfilm.

2. Description of the Related Art

In recent years, semiconductor devices have become faster and morehighly integrated and resistance-capacitance (RC) coupling delays havebecome a large factor in signal processing time. RC delays can bedecreased by reducing wiring capacitance. One way to do this is to uselow dielectric constant materials such as fluorine-doped SiO₂, porousSiO₂, an organic film or a porous film, etc. However, these materialshave not been put to practical use because of problems such asprocessing difficulty and insufficient heat-resistance, which canincrease the complexity of the integration processes and lower devicereliability. Although, fluorinated silicon glass (FSG) is in productionfor 130 nm node technology, but for 90 nm and smaller nodes, low-kdielectrics with k≦3 are desired for manufacturing future semiconductordevices.

It is projected that high volume manufacturing of faster logic and otherdevices with 45 nm or lower nodes interconnect structures will requireextreme low-k, such as k≦2.4.

The low-k interlayer dielectrics (ILDs) for 65 nm or lower nodes requirenot only low k values but also superior mechanical properties, thermalstability, and applicability to integration processes with copper forDual Damascene structures. These integration processes are disclosed inU.S. Pat. No. 6,440,838 and U.S. Pat. No. 6,440,861, for example.Further, it is preferable to adapt currently available materials, tools,and apparatuses to high volume manufacturing.

SUMMARY OF THE INVENTION

One approach to meet the above requirements is to create porosity indielectric films deposited by SOD (spin-on-dielectrics) or CVDtechniques. For SOD materials, the starting materials may be oxide basedsilica materials or organic polymers. A sacrificial porogen material isused along with the main ILD material during film deposition steps.Using thermal or other techniques, the sacrificial material can beremoved. However, this approach has disadvantages: The depositeddielectric layer has a very high porosity (e.g., >30%) with bimodal ortrimodal pores with pore sizes ranging from 2 nm to 9 nm or higher.Thus, mechanical properties of the layer are very low, particularlyhardness and cohesive strength. Also, because of large pores, new andcostly processes may be required for the Dual Damascene integration withcopper. This processes may result in poor yields and also pose very highchallenge for successful integration with copper. For CVD depositedILDs, one of the starting dielectric material could be oxygen-dopedsilicon glass (OSG), such as Aurora™ low-k film (ASM Japan, Tokyo), thathas a dielectric constant of 3.05 or less, and use of a suitableporogen/sacrificial material which is to be removed is required.

An alternative approach to manufacture extreme low-k dielectric filmswith k<2.4 is to provide air gaps in the dielectric films themselves.The present invention relates to ELK (extreme low-k) dielectric filmswith air gaps generated during integration steps. The present inventioncan be adapted to SiCO-based films by plasma CVD such as PECVD (plasmaenhanced CVD) including RPCVD (remote plasma CVD) or thermal CVD, or bysputtering or SOG (Spin on Glass).

In an aspect, an embodiment of the present invention provides a methodfor manufacturing a semiconductor device, comprising the steps of: (i)depositing a sacrificial layer on a substrate having a circuit formedthereon; (ii) etching the sacrificial layer except for a portion whereair gaps are to be formed; (iii) depositing a low-dielectric layer overthe substrate until the portion for air gaps is entirely enclosed in thelow-dielectric layer; (iv) etching the low-dielectric layer to form viaholes (“vias”) and trenches therethrough; (v) prior or subsequent tostep (iv), removing the portion for air gaps of the sacrificial layer;and (vi) depositing copper in the vias and trenches which are filledwith the copper contacting a surface of the substrate. By the abovemethod, an ELK film having excellent mechanical properties and excellentapplicability to the Dual Damascene process can effectively and easilybe obtained. In the above, an etch stop layer can be used beforedepositing a low-k film. The purpose of the etch stop layer may have twofolds; as a mechanical support and as a reference etch stop layer forstopping etch.

The present invention includes various embodiments. For example, thepresent invention includes, but is not limited to, the followingembodiments:

In the above, step (iii) may comprise: (iiia) depositing a firstlow-dielectric layer over the substrate until the first low-dielectriclayer and the portion for air gaps are of equal height; and (iiib)depositing a second low-dielectric layer on the first low-dielectriclayer and the portion for air gaps.

The substrate may further include a cap layer on which the sacrificiallayer deposits, wherein step (ii) further includes etching the caplayer. Further, the substrate may further include a wiring layerunderneath the cap layer, wherein the wiring layer is connected to thecopper.

The sacrificial layer may be made of an organic polymer, such asbenzocyclobutene (BCB). When using an organic polymer, step (v) may beselective etching (or selective thermal removal) based on etchingtemperature (e.g., BCB's decomposition temperature is below 400° C.).For example, the etching temperature is 400° C. or lower, depending onthe type of sacrificial layer and the type of dielectric layer.

When using multiple low-dielectric layers, the first low-dielectriclayer may have a dielectric constant of 3.5 or less, preferably 3.0 orless, further preferably 2.5 or less, and the last low-dielectric layermay have a dielectric constant of 4.0 or less, preferably 3.0 or less,further preferably 2.7 or less. Such a low-dielectric layer is usefulespecially for 45 nm node device manufacturing. These layers are porous,and for example, Aurora™ 2.7 low-k film (ASM Japan) may have adielectric constant of approximately 3.05-2.7 and a porosity ofapproximately 6-7%, and Aurora™ 2.6-2.4 film (ASM Japan) may have adielectric constant of approximately 2.6-2.4 and a porosity ofapproximately 15-16%. In other embodiements, Aurora™ low-k film with k3.05-2.7 and Aurora™ ULK films with k 2.6-2.4 are compressive filmsdeposited preferably by CVD methods. The Aurora™ ULK films are depositedby a combination of suitable precursor such as DMDMOS with DVDMS or anyother oxygen containing molecules, such as, oxygen, H₂O₂, THF, cyclic orlinear alcohols, acids, ethers, and lactones.

The air gaps in the low-dielectric layer may be formed between adjacentvias to reduce the dielectric constant from a range of e.g., 2.4-2.9without air-gaps (including 2.5, 2.6, 2.7, and 2.8) to e.g., 1.7-2.4with air gaps (including 1.8, 1.9, 2.0, 2.1, 2.2, and 2.3). The vias andthe air gaps may be substantially of equal height. The height of theportion for air gaps may be in the range of 1 nm to 50 nm.

The above method may be conducted using a plasma CVD chamber.

In another aspect, an embodiment of the present invention provides asemiconductor device having a porous structure comprising: (a) asubstrate on which a wiring layer is formed; (b) a low-dielectric layerhaving a porosity of 5% to 30% (preferably 10-20%) and further havingvoids or air-gaps, said low-dielectric layer having vias and trenchesformed therethrough; (c) a contact layer of copper with which the viasand trenches are filled, said contact layer is in contact with thewiring layer and an upper surface of the contact layer is exposed fromthe dielectric layer. The air-gaps are simply voids and may be filledwith air, although the type of fluid present in the air-gaps is notlimited and may depend on the surrounding environment.

This aspect of the present invention includes, but are not limited to,the following embodiments:

The low-dielectric layer and the contact layer may be laminated multipletimes.

The low-dielectric layer may include air gaps wherein the vias and theair gaps may be substantially of equal height. The material of thelow-dielectric layer may have a dielectric constant of 2.95 or less.

For purposes of summarizing the invention and the advantages achievedover the prior art, certain objects and advantages of the invention havebeen described above. Of course, it is to be understood that notnecessarily all such objects or advantages may be achieved in accordancewith any particular embodiment of the invention. Thus, for example,those skilled in the art will recognize that the invention may beembodied or carried out in a manner that achieves or optimizes oneadvantage or group of advantages as taught herein without necessarilyachieving other objects or advantages as may be taught or suggestedherein.

Further aspects, features and advantages of this invention will becomeapparent from the detailed description of the preferred embodimentswhich follow.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1(a) to 1(f) are cross sections of an embodiment illustrating amethod for producing a porous structure with air-gaps in a semiconductordevice.

FIGS. 2(a) to 2(f) are cross sections of another embodiment illustratinga method for producing a porous structure with air-gaps in asemiconductor device.

FIGS. 3(a) to 3(g) are cross sections of still another embodimentillustrating a method for producing a porous structure with air-gaps ina semiconductor device.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

As described above, in an aspect, the present invention provides amethod for manufacturing a semiconductor device, which method can beperformed using any suitable plasma CVD chambers which can be operatedas one operation system. This is an advantage of the present invention.However, chambers specifically designed for respective steps can beused. The method is suitable for any Damascene process, especially theDual Damascene process which is described in U.S. Pat. No. 6,440,838 orU.S. Pat. No. 6,440,861, for example, the disclosure of which isincorporated herein by reference in its entirety.

An embodiment comprises the steps of: (i) depositing a sacrificial layeron a substrate having a circuit formed thereon; (ii) etching thesacrificial layer except for a portion where air gaps are to be formed;(Add the comment written above for etch stop layer option) (iii)depositing a low-dielectric layer over the substrate until the portionfor air gaps is entirely enclosed in the low-dielectric layer; (iv)etching the low-dielectric layer to form vias and trenches therethrough;(v) prior or subsequent to step (iv), removing the portion for air gapsof the sacrificial layer; and (vi) depositing copper in the vias andtrenches which are filled with the copper contacting a surface of thesubstrate. The purpose of the etch stop layer may have two folds; as amechanical support and as a reference etch stop layer for stopping etch.

Step (iii) may comprise multiple steps to form multiple low-k layers.For example, step (iii) includes: (iiia) depositing a firstlow-dielectric layer over the substrate until the first low-dielectriclayer and the portion for air gaps are of equal height; and (iiib)depositing a second low-dielectric layer on the first low-dielectriclayer and the portion for air gaps. The number of layers may not belimited to two and can be more than two including 3, 4, and 5.

An etch stop layer can be formed between the first low-dielectric layerand the second low-dielectric layer.

When using multiple low-dielectric layers, the first low-dielectriclayer may have a dielectric constant of 2.75 or less (in an embodimentin a range of 2.4 to 2.9), and the last low-dielectric layer may have adielectric constant of 4 or less (including a range of 2.4 to 4). Thelow-dielectric layer may be made of non-doped silicon glass (NSG),phosphate-doped silicon glass (PSG), boron phosphate-doped silicon glass(BPSG), fluorine-doped silicon glass (FSG), silicon-containing carboncompounds, OSG or CDO, organo silicon, or siloxan polymer, etc. Siloxanpolymers can effectively be used as disclosed in U.S. Pat. No. 6,455,445issued Sep. 24, 2002, U.S. Pat. No. 6,352,945 issued Mar. 5, 2002, U.S.Pat. No. 6,383,955 issued May 7, 2002, U.S. Pat. No. 6,410,463 issuedJun. 25, 2002, and U.S. Pat. No. 6,432,846 issued Aug. 13, 2002,disclose material gases which are also usable in the present invention.The disclosure of each U.S. patent application is herein incorporated byreference in its entirety.

In the above, the dielectric constant is measured prior to the formationof air gaps; i.e., the dielectric constant of the material itself in theform of a film formed on a substrate.

The low-dielectric layer can be composed of a single layer which may bemade of any of the foregoing. The thickness of the dielectric layer(s)in total may be in the range of 1 nm to 1000 nm (preferably 1 nm to 500nm). When using two layers, the first layer may have a thickness of 1 nmto 10 nm, whereas the second layer may have a thickness of 1 nm to 300nm.

The low-dielectric layer including air-gaps or voids may have adielectric constant of 2.4 or less, preferably 2.2 or less (including arange of 1.7 to 2.5).

The sacrificial layer may be made of any suitable material havingproperty allowing selective etching. That is, the sacrificial layer isselectively etched while the low-dielectric layer and othernon-sacrificial layers are substantially not etched. Preferably, thematerial is CVD deposited so that semiconductor devices can bemanufactured using a single operation system which may comprise multipleprocess chambers. In an embodiment where PECVD is used, the material maybe hydrocarbon or an organic polymer such as benzocyclobutene (BCB),aromatic or aliphatic hydrocarbons with or without any oxygen ornitrogen attached thereto. The formation of the sacrificial layer mayalso be conducted based on the foregoing U.S. patents. In anotherembodiment where a spin-on method is used, BCB, polyadamentane,polyhydrocarbons, polyethers, polylactones, and the like can be used.

When using an organic polymer, step (v) may be selective etching basedon etching temperature at which the sacrificial layer material isselectively decomposed thermally. For example, the etching temperature(i.e., the material's thermal decomposition temperature) is 400° C. orlower (in an embodiment in a range of 150° C. to 425° C.), depending ona combination of the type of sacrificial layer and the type ofdielectric layer. For example, a hydrocarbon polymer such as BCB isdecomposed at a temperature of 400° C. or lower because the compound hasalkylene linkages which are very prone to thermal decomposition at atemperature of approximately 375° C.. When the sacrificial layermaterial is decomposed, it may become in gaseous form at thedecomposition temperature, so that the material can penetrate throughthe porous dielectric layer, accomplishing removal of the sacrificialmaterial.

The material of the sacrificial layer may be subjected to selectivethermal treatment and other etching treatment with an etching gas suchas fluorine-containing hydrocarbon, oxidative and nitrogen containinghydrocarbon at a pressure of 100 to 1000 Pa, for example. The thicknessof the sacrificial layer may be in the range of 1 nm to 1000 nm(preferably 1 nm to 100 nm).

In an embodiment, after the sacrificial layer is deposited, the layer issubjected to etching except for a portion for forming air gaps or voidsin the low-dielectric layer. This etching can be achieved by currentAurora™ low-k film established chemistries, such as, combinations ofAr/O₂/CF₄/CH₂F₂ for SiO₂ and SiC, Ar/O₂/C₄F₈/N₂/CH₂F₂ for Aurora™trenches and vias, Ar/O₂/CF₄/CH₂CF₂ for barrier dielectric layers, forexample. The dielectric layer has a porosity of 5-30% (including a rangeof 10% to 20%) so that the sacrificial layer material in gaseous formcan easily be removed through the pores without an opening purposelyformed in an etch stop layer or cap film layer. If the porosity is toohigh, the mechanical strength may suffer. The portion for air-gaps isformed in a pattern. The pattern is composed of aligned small pieces(projections) to form an air-gap structure in the low-dielectric layer.The shape of each projection for an air gap or a void may vary, and thecross-section may be a circle, oval, triangle, rectangle, or the like.The height and width of each projection may be 0.5 nm to 500 m(including a range of 1 nm to 200 nm) and 0.5 nm to 1000 nm (including arange of 0.5 nm to 500 nm), respectively. The pattern is configured toposition the projections so that vias can be formed between theprojections. The vias to be formed and the air gaps may be substantiallyof equal height. In an embodiment, the distribution of air-gaps is suchthat the dielectric constant of the dielectric layer is reduced from arange of 2.4-2.9 to a range of 1.7-2.4, for example, or reduced by0.4-0.7. In an embodiment, the dielectric constant of the dielectriclayer may be as high as 3.0-3.5 and reduced to 2.5-3.0, for example.

The substrate may further include a cap layer on which the sacrificiallayer deposits, wherein step (ii) described above further includesetching the cap layer. Further, the substrate may further includes awiring layer underneath the cap layer, wherein the wiring layer isconnected to the copper. These layers can be formed by any suitablemethods.

In an embodiment, the cap layer may be either of polysilicon(polycrystal silicon), amorphous silicon, SiN, SiON, SiO, an organicfilm or a porous film, which has a thickness of 1 nm to 100 nm.

In an embodiment, a method of manufacturing a semiconductor devicecomprises forming an interlayer insulator in the form of a porousstructure with air-gaps.

In another aspect, an embodiment of the present invention provides asemiconductor device having a porous structure comprising: (a) asubstrate on which a wiring layer is formed; (b) a low-dielectric layerhaving a porosity of 5% to 30% (including 6-25%) and having air-gaps orvoids, said low-dielectric layer having vias and trenches formedtherethrough; (c) a contact layer of copper with which the vias andtrenches are filled, said contact layer is in contact with the wiringlayer and an upper surface of the contact layer is exposed from thedielectric layer.

The present invention will be explained below with reference todrawings. The present invention includes various embodiments and shouldnot be limited to the following embodiments.

Embodiments are illustrated in FIGS. 1-3. FIGS. 1(a) to (f) are crosssections illustrating a method for forming a porous structure withair-gaps in a semiconductor device. In FIG. 1(a), a wiring layer 2 isformed on a semiconductor substrate 1 (made of copper, for example) Thewiring layer 2 can be formed by ECD/ECMD copper deposition usingexisting tool and process technology followed by CMP using existingtools and process technologies. The wiring layer 2 can also be formed byMOCVD copper deposition, followed by CMP polishing.

On top of the wiring layer 2 and the substrate 1, a cap film layer 3(made of SiC, SiN, SiCN, SiCO, for example) is formed by PECVD or SODdeposition using existing tools and process technology at a thickness of5 nm to 100 nm. A sacrificial layer 4 (made of BCB, for example) canthen be formed thereon by PECVD or SOD using any suitable methodsincluding existing tools and process technology.

In FIG. 1(b), after placing a mask (not shown), the sacrificial layer 4is patterned and etched except for portions (projections) where air gapsare to be formed. The projection is cylindrical and has a height of 1 nmto 200 nm, a diameter of 25 nm to 65 nm, and the distance between theadjacent projections is 50 nm to 500 nm. This process can be conductedby plasma etching. As a result, only the portions 5 for air gaps areleft on the cap film layer 3. The height of the portions 5 is to beequal to the height of via holes 8.

In FIG. 1(c), a low-dielectric layer 6 (made of SiCO or FSG or oxidefilms, for example) is formed so that the projections 5 are entirelycovered with the low-dielectric layer 6 and further a layer wheretrenches 7 are to be formed is formed. The low-dielectric layer 6 mayhave a dielectric constant of 2.4 to 4, hardness of 1 GPa to 6 GPa,modulus of 4 GPa to 30 GPa, and stress is preferably compressive. Afterforming the low-dielectric layer 6, the top of the layer is polished oretched to level the top surface. The low-dielectric layer is required tobe stable as compared with the sacrificial layer with respect to, e.g.,resistance against an etching fluid and/or thermal resistance so thatthe sacrificial layer can effectively be removed without the occurrenceof unwanted etching to the low-dielectric layer.

In FIG. 1(d), via holes 8 and trenches 7 are formed in thelow-dielectric layer 6. The holes can be formed by plasma etching. Thetrenches can be formed by plasma etching.

FIG. 1(e), the projections 5 are etched and removed to form air gaps orvoids 9 by thermal treatment at 150° C. to 425° C.. The low-dielectriclayer 6 has mechanical and thermal stability so that only theprojections 5 can be selectively etched. The projections 5 aredecomposed at a temperature of 150° C. to 425° C., for example, andusing an etching gas (e.g., hydrogen, and fluorine compound), the airgaps 9 can be cleaned. The stable temperature of the low-dielectriclayer may be 430° C. to 475° C. higher than the melting temperature ofthe sacrificial layer. In order to remove the melt projections from thelow-dielectric layer 6. An Aurora™ low-k film (ASM Japan) has ahomogeneous porosity of approximately 7% and Aurora™ 2.4 has a porosityof approximately 17%. These porosity values are enough to remove thedecomposed BCB gases. As a result, the dielectric constant of thelow-dielectric layer 6 is reduced.

In FIG. 1(f), the vias and the trenches are filled with copper 10 forconnection. Any suitable method for this step can be employed.

In the above, the step indicated in FIG. 1(d) and the step indicated inFIG. 1(e) can be conducted in the reversed sequence as shown in FIG.2(a) through FIG. 2(f). The steps indicated in FIGS. 2(a), 2(b), 2(c),and 2(f) correspond to those indicated in FIGS. 1(a), 1(b), 1(c), and1(f), respectively. The steps indicated in FIGS. 1(d) and 1(e) arereversed as in FIGS. 2(e) and 2(d).

FIGS. 3(a) through 3(g) show another embodiment. In this embodiment, afirst low-dielectric layer used for forming vias is different from asecond low-dielectric layer used for forming trenches. In an embodiment,the second low-dielectric layer has a lower dielectric constant than thefirst low-dielectric layer in order to reduce inter or intra linecapacitance. In the previous embodiment shown in FIGS. 1 and 2, the airgaps are formed in the layer wherein the vias are formed, although thelayer continues and deposits until the thickness of the layer issufficient for forming the trenches. However, the air gaps can be formedin the layer wherein the trenches are formed, or through the layer,wherein the height of the air gaps is greater than the height of thevias. In the embodiment shown in FIG. 3, because the first layer whereinvias are formed is different from the second layer wherein trenches areformed, the height of the air gaps may not be greater than the height ofthe vias (although the height of the air gaps can be lower than theheight of the vias).

The steps indicated in FIGS. 3(a), 3(b), and 3(g) correspond to thoseindicated in FIGS. 1(a), 1(b), and 1(f), respectively. In FIG. 3(c), afirst low-dielectric layer 20 is formed, followed by polishing oretching the top surface to level the surface. The first low-dielectriclayer can be made of Aurora™ ULK (ultra low k) film and may have adielectric constant of 2.4 to 2.7 (including a range of 2.4 to 2.6).Further, the layer may have good mechanical properties, e.g., a hardnessof 1 GPa to 1.2 GPa. The first low-dielectric layer can be the same asor different from the low-dielectric layer used in FIG. 1 or 2.

In FIG. 3(d), a second low-dielectric layer 21 is deposited on top ofthe first low-dielectric layer 20. In this embodiment, the secondlow-dielectric layer 21 is different from the first low-dielectriclayer, and may have a lower dielectric constant than the firstlow-dielectric layer as desired for devices. The stack dielectricconstant after integration may be low. The second low-dielectric layermay also have lower mechanical characteristics, e.g., a hardness of 1GPa to 2 GPa. In another embodiment, the second low-dielectric layer mayhave a higher dielectric constant than the first low-dielectric layer,and higher mechanical characteristics in the case where highermechanical characteristics of the stack is required. The secondlow-dielectric layer can be the same as or different from thelow-dielectric layer indicated in FIG. 1 or 2. The low-dielectric layerscan be deposited by any suitable methods including plasma CVD (includingRP-CVD and PECVD) and thermal CVD, etc. The methods disclosed in theaforesaid U.S. patents, the disclosure of which is incorporated hereinby reference in their entirety, can be used for this purpose.

In an embodiment, a cap film layer (made of SiO₂ or SiON, for example)can be formed between the first low-dielectric layer 20 and the secondlow-dielectric layer 21 at a thickness of 1 nm to 5 nm so that thedielectric top surface is hydrophilic for cleaning after CMP and alsothis layer can be used as a CMP etch stop layer.

The steps indicated in FIGS. 3(e), 3(f), and 3(g) correspond to thoseindicated in FIGS. 1(d), 1(e), and 1(f), respectively. The etchingconditions for the first low-dielectric may be different from those forthe second low-dielectric layer due to the different materials.

As with the steps indicated in FIG. 2, the sequence of steps indicatedin FIGS. 3(e) and 3(f) can be reversed, wherein the removal step of thesacrificial layer is conducted prior to the via and trench etching step.This reverse sequence may be preferable in an embodiment becauseunwanted etching on the inner surfaces of the vias and trenches can beavoided.

The number of low-dielectric layers is not limited to two, and anydesirable layers can be used. In an embodiment, the characteristics ofthe layer can be gradually changed from the bottom to the top.

In the above steps, the sacrificial layer and the low-dielectric layercan be deposited by a single CVD tool. For example, if the CVD tool is acluster tool with at least three chambers, one chamber can be used forremoving the sacrificial layer thermally. In order to accommodate etchstop and cap layers, the cluster tool may have an additional chamber forthat purpose (i.e., total four chambers).

According to the present invention, an effective porous structure withair-gaps can effectively be formed. This process can effectively applyto interconnection layers. The various embodiments provide a number ofadvantages, including improved selectivity, higher process stability,reduced production costs and increased yield.

It will be understood by those of skill in the art that numerous andvarious modifications can be made without departing from the spirit ofthe present invention. Therefore, it should be clearly understood thatthe forms of the present invention are illustrative only and are notintended to limit the scope of the present invention.

1. A semiconductor device having a hollow structure comprising: asubstrate on which a wiring layer is formed; a low-dielectric layerhaving a porosity of 6% to 25%, said low-dielectric layer having viasand trenches formed therethrough and having voids between adjacent vias;and a contact layer of copper with which the vias and trenches arefilled, wherein the contact layer is in contact with the wiring layerand an upper surface of the contact layer is exposed from the dielectriclayer.
 2. The semiconductor device according to claim 1, wherein thelow-dielectric layer having voids has a dielectric constant of 2.3 orless.
 3. The semiconductor device according to claim 1, wherein thelow-dielectric layer and the contact layer are laminated multiple times.4. The semiconductor device according to claim 1, wherein the voids areair gaps, and the vias and the air gaps are substantially of equalheight.
 5. The semiconductor device according to claim 1, wherein thematerial of the low-dielectric layer has a dielectric constant of 2.9 orless.
 6. The semiconductor device according to claim 1, wherein thelow-dielectric layer is comprised of a first low-dielectric layer formedon the substrate and a second low-dielectric layer formed on the firstlow-dielectric device.
 7. The semiconductor device according to claim 6,further comprising an etch stop layer between the first low-dielectriclayer and the second low-dielectric layer.
 8. The semiconductor deviceaccording to claim 1, wherein the substrate further includes a cap layeron which the low-dielectric layer is formed.
 9. The semiconductor deviceaccording to claim 6, wherein the first low-dielectric layer has adielectric constant of 3.0 or less.
 10. The semiconductor deviceaccording to claim 9, wherein the first low-dielectric layer hascompressive stress.
 11. The semiconductor device according to claim 6,wherein the first low-dielectric layer is deposited by a combination ofdimethyldimethoxysilane (DMDMOS) with divinyldimethylsilane (DVDMS) oroxygen-containg molecules.
 12. The semiconductor device according toclaim 6, wherein the second low-dielectric layer has a dielectricconstant of 2.6 or less.
 13. The semiconductor device according to claim12, wherein the second low-dielectric layer has compressive stress. 14.The semiconductor device according to claim 6, wherein the secondlow-dielectric layer is deposited by a combination ofdimethyldimethoxysilane (DMDMOS) with divinyldimethylsilane (DVDMS) oroxygen-containg molecules.
 15. The semiconductor device according toclaim 1, wherein the height of the voids is in the range of 1 nm to 100nm.
 16. The semiconductor device according to claim 1, wherein the viasand the voids are substantially of equal height.